The present invention generally relates to memory cards and, more particularly, to a memory card which is operated in response to a chip select signal as a negative logical signal to prevent erroneous operation of the card when inserted into and pulled out from a data processing device such as a reader/writer as a main device.
The present invention also concerns data processing systems which comprises a memory card and a data processing device and, in particular, a data processing system which is operated in response to two chip select signals of positive and negative logics when a memory card is inserted into the data processing device and wherein as soon as the data processing device as a main device is reset, the operation of the memory card is stopped to prevent erroneous operation of the memory card.
A memory card usually comprises a decoder and a plurality of memory ICs (in other words, integrated circuits or memory elements having a memory function) which are arranged so that the decoder selects one of the plurality of memory ICs.
In this sort of prior art memory card having a plurality of memory ICs, the logic of a chip select signal CS to the memory card is determined by the configuration of the memory ICs. In particular, in the case where the memory card is arranged so as to be operated (become significant) when the chip select signal is at its low ("L") level, the card tends to be highly subjected to an erroneous writing operation in the unstable period of a power supply voltage at the time of inserting the memory card into the data processing device or at the time of pulling out from the data processing device because the power supply voltage abruptly drops at that time.
More in detail this is because terminals for reception of such control signals as chip select signals and read/write signals are pulled up with respect to an external power supply voltage Vcc and further an enable signal output terminal to the decoder is also pulled up directly or indirectly, for which reason the power voltage becomes unstable and the enable signal and the external chip select signals are directly affected.
FIG. 1 is a timing chart for explaining the state of various signals at the time of inserting the memory card into the data processing device. It will be seen from the drawing that, until the memory card is inserted into the data processing device to such an extent that a connector provided on the memory card is fully connected with a connector provided to the data processing device, chattering takes place in the beginning part of a power voltage Vcc as shown by (a) in FIG. 1. The chattering part of the power voltage Vcc causes an enable signal (significant for "L" level) on the decoder, external chip select signal and a read/write signal is also chattered, as shown by (b), (c) and (d) in FIG. 1. The chattering phenomenon results in that there occurs when the chip select signal is at "L" level and simultaneously the read/write signal is at "L" level, at which time the data stored in the memory ICs may be undesirably rewritten because the write conditions to the memory ICs are satisfied. In the drawing, reference symbol t denotes a time period from the beginning of supply of the power to the end of the chattering generation period.
Shown in FIG. 2 is a timing chart when the memory card is removed from the data processing device. As will be seen from the drawing, when the memory card is removed to disconnect the connector of the card from that of the data processing device, the externally-supplied power voltage Vcc first drops as shown by (a) in FIG. 2. Under the influence of a drop in the power voltage Vcc, voltages at a chip select signal terminal and at a write control signal terminal drop and the externally-received chip select signal and the read/write control signal drop down to their "L" level, as shown by (c) and (d) in FIG. 2. However, since the enable signal to the decoder is usually generated after a voltage detecting circuit detects a drop in the power supply voltage Vcc, the generation of the enable signal is delayed by the operation time of the voltage detecting circuit is later than a timing when the chip select signal and read/write control signal drop. That is, the enable signal rises to its "H" (high) level at such a timing as shown by (b) in FIG. 2. For this reason, there occurs when the chip select signal and read/write signal are both at "L" level (which period corresponds to P in FIG. 2), that the write conditions to the memory ICs are satisfied and thus the data stored in the memory ICs may be undesirably rewritten.
On the other hand, the data processing device to be inserted with the memory card usually includes a microprocessor (which will be hereinafter sometimes referred as the MPU,) and an initial reset circuit which constantly sends a reset signal to a reset terminal of the MPU unless the power supply voltage is in a predetermined voltage range both at the time of turning ON and OFF the power.
FIG. 3 shows a prior art data processing system which includes a data processing device 20 and a memory card 23, when the card is inserted in the data processing device. More specifically, the data processing device 20 includes an initial reset circuit 21 and an MPU 22. The initial reset circuit 21 incorporates therein a voltage detecting circuit which acts to detect a power supply voltage fed to the data processing device and when the detected voltage is out of the predetermined voltage range both at the time of turning ON and OFF the power, to put the MPU 22 in its reset state. The memory card 23, on the other hand, includes a power voltage detecting circuit 23a for detecting the level of the power voltage supplied from the data processing device to switch between power supplied from the data processing device 20 through a power supply line 24 and power supplied from a battery incorporated therein. In this case, the voltage detection level of the voltage detecting circuit of the initial reset circuit 21 and that of the voltage detecting circuit 23a of the memory card 23 are set independently of each other and thus mutually independently operated.
With such an arrangement, when the power supply voltage Vcc on the power supply line 24 on the side of the data processing device 20 drops down to below the predetermined voltage detection level as shown by (a) in FIG. 4, a reset signal (RST) such as shown by (b) is generated at the initial reset circuit 21 and thus the supply voltage of the power supply line 24 to the memory card 23 also drops. At this time, the MPU 22 is reset by the initial reset circuit 21, but even when the MPU 22 is reset, the memory card 23 remains operative unless the voltage detecting circuit 23a of the memory card 23 detects the drop of the supply voltage. In other words, it is, when the power voltage detecting circuit 23a of the memory card 23 detects a further drop in the power supply voltage Vcc of FIG. 4, (a) to inhibit the generation of the enable signal (significant with "L" level) of FIG. 4, (c) fed to the decoder, that the operation of the memory card 23 is stopped.
Under such a condition, the chip select signal CS and read/write signal R/W sent from the MPU 22 become unstable and there occurs when the chip select signal CS becomes "L" level as shown by (d) in FIG. 4. Accordingly, a writable period is produced between the generation of the reset signal and the generation of the enable signal. Since the write conditions to the memory card 23 are satisfied in the writable period, the data stored in the memory ICs may be undesirably rewritten or erased.